Flex-to-rigid (F2R) is a high-precision micro-assembly platform, that includes flexible polymer interconnects with embedded electrical tracks. Virtually every 3D shape can be constructed out of IC technology in extremely small form factors with F2R.

What is so special about F2R? How is it different from existing technologies?

F2R is designed in such a way, that it can bring complex electronics and sensors functionality to the smallest form factor. It is a semi-flexible integration platform that enables conversion from 2D to 3D assembly. Also, it is a relatively cheap (compared to TSVs) 3D interposer stacking.

F2R represents the next step in the reduction of fine line space and takes over where advanced flex foil technologies stop. F2R also maximizes interconnect density: wafer-level processing means that multiple functionalities can be integrated on the wafer-level.

What are the limiting factors of F2R?

F2R can be executed only using limited choice of substrates and materials: SOI wafers, polyimide (PI) for embedment of the tracks and Al for electrical tracks. Currently there is no option to make line crossings for the electrical track.

What are potential applications areas of F2R?

F2R has been developed by the Philips MEMS Foundry to bring complex electronic imaging functionality to the tip of smart catheters and guide wires. It is, however, just as fit for many other applications that make use of multiple electronic components.

The technology is best suited for applications where miniaturization and simplification of the 3D assembly is critical, as well as when a high density of functional elements is needed. Some application areas include (smart) catheters, micro-needle arrays, implantable devices, neuromodulation devices, wearable devices, and optical elements.

For instance, with F2R it is made possible to place 120 ultrasonic elements in the same space at 60 elements by the conventional methods and have their electrically interconnected predefined at wafer level, hence, omitting assembly steps.

What substrates can be used in F2R?

Both silicon (Si) and silicon on insulator (SOI) are suitable for F2R processing, while glass or other substrates are not.

What metals can be used for the electrical interconnects?

The standard solution for interconnects is AlCu. While there is an established lift-off process for Au, Pt and Ti, their lack of adhesion to poluimide (PI) makes it virtually impossible to use for F2R. For the bond pads Al and postprocessed NiAu, NiPdAu Ccan be standardly used.

What polymers can be used for the interconnects?

Due to the requirements for temperature resistance of some of the processing steps, Polyimide (PI) is the only suitable solution. Parylene has some potential, but lower meting point as well as general complexity of processing, makes this polymer much less suitable.

How easy/possible it is co-execute other process flows in combination with F2R? Are there process steps that are not compatible?

Compatibility with pre-processed CMOS wafers is almost impossible as buried tranches that define circumference (perimeter) of the device must be processed prior any functional elements. However, compatibility with other pre-processed Si wafers can be discussed on a case-to-case basis.

Is F2R compatible with pick-and-place?

Postprocessing of F2R chips can include, but is not limited to flip-chip of other elements, fan-out from high density pitch of F2R to low density pitch of wire connection, integration with, ASIC, capacitors, Electroless plating, nanowiring, UBM stack application.

What is the smallest form factor possible?

The dimensions of the Si islands can be as small as 20×20 um2 with min thickness of 20 um; the standard bending radius of the buried electrical interconnects is 20-50 um; the interconnects were shown to sustain a full “hard fold”. The final 3D design would determine the overall form factor.

Is F2R processing ready for production?

The wafer-level process of F2R is nearly at TRL/MRL 8.  Depending on customer needs and application a short development might be required for customization. Assembly and packaging are always device and application specific, hence, will require specific tooling design to make right form factor and shape, thus MRL could be attributed to level 5.

Is it possible to make more than one interconnects layers?

Within polymer interconnects it is technically possible, as was shown in a feasibility study. However, adding a second interconnect layer might come with limitations to bending radius and elevated tensile stress. With functional Si islands, the only limitation is the desired thickness of the island versus thickness of the electrode.

Si island thickness – is it a constant value or can be different? What are the limitations?

Si island sickness is product dependent and is defined by the active Si layer of BOX wafer; it also depends on required processing precision and CD. The current standard thickness is 20-40 um.

How short/long the electrical interconnects can be?

A straight connection can be in range of um to to 1mm for or longer when daisy chains are made.